Method and apparatus for an easy identification of a state of a DRAM generator controller
US6530051B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 23, 2000 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | Mar 23, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4074
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a controller for controlling a generator system on a memory chip, the controller operates as a state machine in accordance with a state diagram including a plurality of N states. A state storage device is responsive to input signals from a transition arrangement including a 1-out-of-N code indicating a change in the state diagram from a current state to a next state of the plurality of N states. The state storage device generates a revised plurality of N state output signals comprising a true State signal and a complementary true State signal for the next state of the plurality of N states. The state storage device is also responsive to an asynchronous Reset signal received from an external source for generating a Reset and a complementary Set output signal. A state identification circuitry is responsive to a selectively applied activation signal for inhibiting the output of the revised plurality of N state signals from the state storage device and sequentially reading out the plurality of N state signals currently stored in the state storage device. The the 1-out-of N-code forming the plurality of N state signals are used to determine which state of the state diagram the contro…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.