Method and apparatus for predicting an operational lifetime of a transistor
US6530064B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2000 |
| Grant date | Mar 4, 2003 |
| Priority date | — |
| Expiry date | Jun 5, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An operational lifetime, and also performance characteristics, can be accurately predicted for an experimental transistor design (10) and a specified set of fabrication process conditions (117), without actually fabricating and testing a physical transistor made according to the particular design data and process conditions. With respect to the prediction of an operational lifetime, the operational lifetime can be expressed as a function of the size of a gate overlap (12) of the transistor, and this relationship is valid throughout a selected semiconductor technology for which the transistor is designed. The size of the gate overlap is determined by selecting a combinations of values for two process conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.