Method and structure for high-voltage device with self-aligned graded junctions
US6531366B1 · kind B1 · utility
8Cited by
5References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 12, 2001 |
| Grant date | Mar 11, 2003 |
| Priority date | — |
| Expiry date | Jul 12, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0223
Abstract
A method of fabricating a semiconductor device (300) is disclosed. A low energy ion implantation (318) may form low voltage source and drain regions in a low voltage region (402-3) of a substrate. A low energy implant may also form a portion of source and drain regions in a high voltage region (402-2). A high energy ion implantation (322) may complete the formation of high voltage transistors in a high voltage region (402-2). A high voltage gate structure (418-2) may be exposed during a high energy ion implantation and mask a channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.