Overlay shift correction for the deposition of epitaxial silicon layer and post-epitaxial silicon layers in a semiconductor device
US6531374B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2001 |
| Grant date | Mar 11, 2003 |
| Priority date | — |
| Expiry date | Aug 10, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
Correction of overlay shift of an epitaxial silicon layer deposited on a semiconductor wafer, and of post-epitaxial silicon layers subsequently deposited, is disclosed. When an epitaxial silicon layer of a given thickness is deposited, the zero mark coordinates for the deposition are shifted relative to alignment marks on the wafer by a distance based on the thickness of the layer. The distance is preferably proportional to the thickness of the epi layer. This prevents overlay shift of the epi layer. For post-epitaxial silicon layers subsequently deposited, preferably except for the first post-epi layer, a clear out process is initially performed to maintain the alignment marks on the semiconductor wafer. In this way, overlay shift, or misalignment, of the post-epi layers is also prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.