Borderless gate structures

US6531724B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Toshiharu Furukawa · South Burlington, US
• Mark C. Hakey · Saint Albans, US
• Steven J. Holmes · Colchester, US
• David V. Horak · South Burlington, US
• Paul A. Rabidoux · Winooski, US

Key dates

• Filing date: Oct 10, 2000
• Grant date: Mar 11, 2003
• Expiry date: Oct 10, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76895
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for forming a gate conductor cap in a transistor comprises the steps of: a) forming a polysilicon gate conductor; b) doping the polysilicon gate; c) doping diffusion areas; and d) capping the gate conductor by a nitridation method chosen from among selective nitride deposition and selective surface nitridation. The resulting transistor may comprise a capped gate conductor and borderless diffusion contacts, wherein the capping occurred by a nitridation method chosen from among selective nitride deposition and selective surface nitridation and wherein a portion of the gate conductor is masked during the nitridation method to leave open a contact area for a local interconnect or a gate contact.