Semiconductor device having reduced interconnect-line parasitic capacitance
US6531776B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2001 |
| Grant date | Mar 11, 2003 |
| Priority date | — |
| Expiry date | Aug 29, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device having reduced interconnect-line parasitic capacitance is provided. The method includes the following steps. First, a substrate is provided and a plurality of interconnect lines are formed on the substrate. A barrier layer is then formed. Next, the barrier layer is hardened and thinned so as to make the barrier layer having a thin-film attribute. Following that, a separation layer is formed by filling the space between and above the interconnect lines with a dielectric. Then, the dielectric is foamed. After that, an insulating layer is formed. Finally, the dielectric is condensed such that air gaps are formed in the separation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.