Microstrip package having optimized signal line impedance control
US6531932B1 · kind B1 · utility
11Cited by
9References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2001 |
| Grant date | Mar 11, 2003 |
| Priority date | — |
| Expiry date | Jul 20, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a microstrip package to optimize signal trace impedance control is disclosed. The method includes patterning a plurality of signal traces on a multilayer substrate, and patterning a plurality of guard traces on the multilayer substrate, that are interspersed alternately among the signal traces to provide noise shielding between the signal traces. In a further embodiment, the traces are patterned on the substrate with a width that is adjusted at different locations based on the presence the guard traces to enable the package to meet a particular impedance requirement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.