Combined floating-point logic core and frame buffer
US6532018B1 · kind B1 · utility
12Cited by
14References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 19, 1999 |
| Grant date | Mar 11, 2003 |
| Priority date | — |
| Expiry date | Apr 19, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T15/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for graphical processing. A logic core to perform pixel fragment manipulation and processing is instantiated on a single substrate with one or more memory units. The memory units are dynamically segmentable into frame buffer and texture memory. Because the logic core is on the same substrate as the memory units, the bandwidth between the core and the memory is greatly increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.