Cell interconnect delay library for integrated circuit design
US6532576B1 · kind B1 · utility
10Cited by
4References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2001 |
| Grant date | Mar 11, 2003 |
| Priority date | — |
| Expiry date | Jun 14, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for characterizing cell interconnect delay is disclosed that may be included in a library for use with logic design tools. A method of characterizing cell interconnect delay includes the steps of (a) receiving as inputs a plurality of input ramptimes and a plurality of interconnect lengths for a selected cell, and (b) calculating an output ramptime and a total cell delay including a cell delay and an interconnect delay for each of the plurality of input ramptimes for each of the plurality of interconnect lengths for the selected cell from the inputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.