Method of minimizing leakage current and improving breakdown voltage of polycrystalline memory thin films
US6534326B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2002 |
| Grant date | Mar 18, 2003 |
| Priority date | — |
| Expiry date | Mar 13, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/31
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A polycrystalline memory structure is described for improving reliability and yield of devices employing polycrystalline memory materials comprising a polycrystalline memory layer, which has crystal grain boundaries forming gaps between adjacent crystallites overlying a substrate. An insulating material is located at least partially within the gaps to at least partially block the entrance to the gaps. A method of forming a polycrystalline memory structure is also described. A layer of material is deposited and annealed to form a polycrystalline memory material having gaps between adjacent crystallites. An insulating material is deposited over the polycrystalline memory material to at least partially fill the gaps, thereby blocking a portion of each gap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.