Gate-controlled, graded-extension device for deep sub-micron ultra-high-performance devices
US6534351B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 2001 |
| Grant date | Mar 18, 2003 |
| Priority date | — |
| Expiry date | Mar 19, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A gate-controlled device includes an inverted-T gate which overlaps lightly doped, shallow extension regions formed in an underlying base layer. Spacers are included on the sides of the gate, and source/drain regions are formed in the base layer in non-overlapping relationship with the gate layer. This device outperforms conventional devices in terms of performance. Lower external resistance is achieved by forming a gate-controlled inversion channel over at least a portion of the shallow LDD extensions, and by making the shallow LDD extensions graded (or sloped) towards the deep source/drain regions. Also, forming portions of the gate underneath the spacers, electrical gate control of the shallow LDD junctions is made possible. This advantageously reduces the series resistance of the device and increases drive current, both of which translate into improved device performance with no increase in gate-to-source/drain parasitic capacitance. A method for making the gate-controlled device includes forming the source/drain regions and shallow LDD extensions before deposition of the gate. This advantageously allows high-k dielectrics to be used in the device with reduced temperature stabi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.