Method for fabricating a MOSFET device
US6534352B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 21, 2001 |
| Grant date | Mar 18, 2003 |
| Priority date | — |
| Expiry date | Jun 21, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28167
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a MOSFET fabrication method capable of forming an ultra shallow junction while ensuring stability in controlling threshold voltage. The disclosed method relies on the use of a sacrificial gate structure to form LDD regions and the addition of side wall spacers to form source/drain regions, followed by the deposition of an interlayer insulating film. The sacrificial gate structure is then removed to form a groove in the interlayer insulating film that exposes a portion of the silicon substrate. A sacrificial oxide is grown on the exposed silicon substrate and impurity ions are implanted through the oxide to adjust the threshold voltage. The sacrificial oxide is then removed and replaced by a high quality gate insulating film. A metal gate electrode is then formed in the groove above the gate insulating film, thereby forming a MOSFET device having a metal gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.