Tunnel diode layout for an EEPROM cell for protecting the tunnel diode region
US6534364B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 1997 |
| Grant date | Mar 18, 2003 |
| Priority date | — |
| Expiry date | Sep 7, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/981
Abstract
A tunnel diode construction 12 for an EEPROM device 10, and method for making it are shown. A tank 13 is provided at a surface of a semiconductor substrate 5 containing a doped diffused tunnel region 46. A layer of insulation 38 is provided over the surface of the substrate with a first thickness 48 to provide a tunnel oxide over at least part of the tunnel region and a second, larger, thickness 39 elsewhere. A conducting floating gate 19 is provided above the doped diffused tunnel region 46 and at least part of the tank 13, on the layer of insulation 38. The floating gate 19 extends over the oxide 38 beyond the lateral boundaries of the doped diffused tunnel region 46 in every direction to terminate over the second thickness of oxide 39 over the tank 13. To complete the EEPROM device 10, an MOS transistor 15 having source 21 and drain 27 doped regions provided in the substrate 5, with a portion 29 of the floating gate 19 capacitively coupled to a control gate 25 and extending over at least part of a channel region 28 of the MOS device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.