Dual level contacts and method for forming
US6534389B1 · kind B1 · utility
18Cited by
29References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2000 |
| Grant date | Mar 18, 2003 |
| Priority date | — |
| Expiry date | Mar 9, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76895
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making electrical contacts to device regions in a semiconductor substrate, and the resulting structure, is presented. A first set of borderless contacts is initially formed. This first set of contacts is then contacted by a second series of smaller, upper-level contacts. The second set of contacts also contact the gate of the device. The structure which results has a form wherein there are stacked contacts to the diffusion layer, and a single level contact to the device gate. The structure further provides local interconnectability over gate structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.