Semiconductor wafer designed to avoid probed marks while testing
US6534853B2 · kind B2 · utility
72Cited by
2References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2001 |
| Grant date | Mar 18, 2003 |
| Priority date | — |
| Expiry date | Jun 12, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/02377
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A semiconductor wafer is disclosed for avoiding probed marks while testing. The wafer has a plurality of metal interconnects, each metal interconnect connecting underlying bonding pad, corresponding contact pad and test pad. Each contact pad being outer electrical connection terminal is connected in series by a metal interconnect between test pad and bonding pad, so that the section of the metal interconnect between bonding pad and contact pad enable be tested during probing the test pad. Furthermore, there is no probing mark on the contact pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.