Voltage boost circuit using supply voltage detection to compensate for supply voltage variations in read mode voltage
US6535424B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2001 |
| Grant date | Mar 18, 2003 |
| Priority date | — |
| Expiry date | Jul 25, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Flash memory array systems and methods are disclosed for producing a supply regulated boost voltage, wherein the application of a supply voltage to a supply voltage level detection circuit (e.g., analog to digital converter, digital thermometer) which is used to generating one or more supply voltage level detection signals from measurement of the supply voltage level applied to the voltage boost circuit, which may be used as a boosted wordline voltage for the read mode operations of programmed memory cells, and wherein the supply voltage level detection signals are applied to a boosted voltage compensation circuit to generate one or more boosted voltage compensation signals which are applied to a voltage boost circuit operable to generate a regulated boosted voltage for a flash memory array of programmed core cells. Thus, a fast compensation means is disclosed for the VCC power supply variations typically reflected in the output of the boost voltage circuit supplied to the word line of the flash memory array, thereby generating wordline voltages during the read mode which are substantially independent of variations in the supply voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.