Testing apparatus for semiconductor memory device
US6535993B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 1999 |
| Grant date | Mar 18, 2003 |
| Priority date | — |
| Expiry date | Dec 16, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5606
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Row faulty bit storage memory corresponding to a spare row circuit and a column faulty bit storage memory corresponding to a spare column circuit are provided independently of each other, and faulty bits of these faulty bit storage memories are counted by a row faulty bit counter and a column faulty bit counter, respectively. Repairability of the faulty row and repairability of the faulty column are determined using the row faulty bit storage memory and the column faulty bit storage memory. A time required for determining repairability of the faulty bit of a semiconductor memory is reduced, and a storage capacity of the faulty bit storage memory is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.