Fault insertion method, boundary scan cells, and integrated circuit for use therewith
US6536008B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 1998 |
| Grant date | Mar 18, 2003 |
| Priority date | — |
| Expiry date | Oct 27, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318541
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A number of fault injection circuits and corresponding methods for injecting correlated, uncorrelated, non-persistent and persisting faults at the primary outputs of boundary scan cells are disclosed. Fault data is loaded in the boundary scan cell update latch of all boundary scan cells at which a fault is to be injected. The fault injection circuits generate a fault inject signal which is applied to the control input of the standard cell output selector, an active signal causing the content of the update latch to be applied to the cell primary output. In order to provide for scan testing of the fault injection circuitry, the boundary scan cell shift and update latches and the fault flag latch (if employed) are provided with hold capability so that the contents of these elements can be controlled and their input captured in accordance with standard scan testing techniques.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.