One-step bumping/bonding method for forming semiconductor packages
US6536653B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 16, 2001 |
| Grant date | Mar 25, 2003 |
| Priority date | — |
| Expiry date | Jan 16, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/0455
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A one-step bumping/bonding process for forming a semiconductor package is disclosed. In the method, a first electronic substrate which has either a plurality of conductive pads or a plurality of recessed openings formed on top of a plurality of apertures through the substrate is first provided and aligned with a second electronic substrate that has a plurality of conductive pads with each aperture aligned to a conductive pad on the second substrate. A plurality of solder balls is then planted on top of the plurality of conductive pads or the plurality of recessed openings on the surface of the first electronic substrate by a pick-and-place technique. Alternatively, a plurality of solder paste may be printed by a thick film stencil printing process similarly in place of the plurality of solder balls. After a solder reflow process, the solder balls placed on top of the apertures is reflown into the apertures forming solder plugs and making electrical connection with the conductive pads on the second electronic substrate thus completing the one-step bumping/bonding process for forming a semiconductor package. The electronic substrate may be either a printed circuit board or a silicon …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.