Method of forming an integrated circuit comprising a self aligned trench

US6537870B1 · kind B1 · utility

Assignee

• Infineon Technologies AG · DE

Inventor

• Hua Shen · Beacon, US

Key dates

• Filing date: Sep 29, 2000
• Grant date: Mar 25, 2003
• Expiry date: Sep 29, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/482

Abstract

An integrated circuit comprising a vertically oriented device formed with a substantially SELF ALIGNED process, in which the trench, active area (e.g., 128, 228), and gate (e.g., 132, 232) of a DRAM cell may be formed using a minimal number of masks and lithographic steps. Using this process, a DRAM cell comprising a vertical transistor and a buried word line (e.g., 132, 232) may be formed. A gate dielectric (e.g., 130, 230) may be disposed adjacent the active area, and the portion of the buried word line adjacent the gate dielectric may function as the vertically oriented gate for the vertical transistor. The DRAM memory cell may comprise one of a variety of capacitors, such a trench capacitor underlying the vertical transistor, or a stack capacitor (e.g., 241) overlying the vertical transistor. When a stack capacitor is used, a buried bit line (e.g., 208) underlying the vertical transistor may also be used.