Semiconductor memory device for reducing damage to interlevel dielectric layer and fabrication method thereof
US6537875B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2001 |
| Grant date | Mar 25, 2003 |
| Priority date | — |
| Expiry date | Sep 5, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/0335
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The semiconductor memory device includes an interlevel dielectric pattern and an adhesive pattern, wherein both the interlevel dielectric and adhesive patterns include a contact hole to expose a semiconductor substrate. The adhesive pattern sufficiently adheres a lower electrode of a capacitor to the interlevel dielectric pattern, and thus prevents damage to the interlevel dielectric pattern during the formation of the capacitor. A conductive plug is disposed within the contact hole and may project higher than the top surface of the adhesive pattern. A leakage current preventive pattern is formed on top of the adhesive pattern and prevents a capacitor dielectric layer from directly contacting the plug to prevent occurrences of leakage current. A lower electrode of a capacitor electrically connected to the plug is formed on the plug.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.