Process for manufacturing a non-volatile memory cell with a floating gate region autoaligned to the isolation and with a high coupling coefficient

US6537879B2 · kind B2 · utility

Assignee

• STMicroelectronics SA

Inventors

• Roberto Bez · Milano, IT
• Emilio Camerlenghi · Bergamo, IT
• Stefano Ratti · San Donato Milanese, IT

Key dates

• Filing date: Jul 6, 2001
• Grant date: Mar 25, 2003
• Expiry date: Jul 6, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B69/00

Abstract

A process for fabricating non-volatile memory cells on a semiconductor substrate includes forming a stack structure comprised of a first polysilicon layer isolated from the substrate by an oxide layer. The first polysilicon layer, oxide layer, and semiconductor substrate are cascade etched to define a first portion of a floating gate region of the cell and at least one trench bordering an active area of the memory cell. The at least one trench is filled with an isolation layer. The process further includes depositing a second polysilicon layer onto the whole exposed surface of the semiconductor, and etching the second polysilicon layer to expose the floating gate region formed in the first polysilicon layer, thereby forming extensions adjacent the above portion of the first polysilicon layer.