High density design for organic chip carriers
US6538213B1 · kind B1 · utility
20Cited by
19References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2000 |
| Grant date | Mar 25, 2003 |
| Priority date | — |
| Expiry date | Feb 18, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10734
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An organic integrated circuit chip carrier for high density integrated circuit chip attach, wherein the contact pads or microvias which provide electrical interconnections to external circuitry are located in a first array pattern, while the plated through holes or through-vias are located in a second array pattern. This allows utilization of wiring channels within the chip carrier in which signal wiring traces can be routed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.