Buffer with stable trip point
US6538466B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 26, 2001 |
| Grant date | Mar 25, 2003 |
| Priority date | — |
| Expiry date | Jul 26, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00384
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An input buffer having a stable trip point over at least process skew and supply voltage variations includes a first inverter stage; a second inverter stage; and an arrangement for compensating for process skew and supply voltage variations. The compensating arrangement is disposed both in the pull-up and pull-down paths, and increases the conductivity of the pull-up path and decreases the conductivity of the pull-down path when the DC trip point of the input buffer falls below nominal. The compensating arrangement also decreases the conductivity of the pull-up path and increases the conductivity of the pull-down path when the DC trip point rises above nominal. The compensating arrangement may include at least one device disposed in each of the pull-up and pull-down paths. The conductivity of these devices may then be controlled by a reference signal that swings about the DC trip point responsive to at least process skew corners and variations in supply voltage. Alternatively, the compensating arrangement may include a first and a second pair of devices of a first and second conductivity type connected in parallel and disposed in the pull-up and pull-down paths. The devices of the …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.