Low jitter transmitter architecture with post PLL filter
US6538499B1 · kind B1 · utility
19Cited by
6References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 9, 2002 |
| Grant date | Mar 25, 2003 |
| Priority date | — |
| Expiry date | Jan 9, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H11/1213
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A post PLL filter is coupled to the output terminal of a phase locked loop. The post PLL filter reduces the jitter of the PLL output clock signal by increasing the Q of the phase locked loop. In addition, some embodiments of the present invention also provides amplitude magnification of the PLL output clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.