Efficient TLB entry management for the render operands residing in the tiled memory
US6538650B1 · kind B1 · utility
12Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2000 |
| Grant date | Mar 25, 2003 |
| Priority date | — |
| Expiry date | Jan 10, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/654
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for efficient translation lookaside buffer (“TLB”) management of three-dimensional surfaces is disclosed. A three-dimensional surface is represented as a square pixel surface. The square-surface representation is stored in a single entry of the TLB.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.