TSOP memory chip housing configuration

US6538895B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Andreas Wörz · Blaustein, DE
• Alfred Gottlieb
• Bernd Römer · Burgau, DE

Key dates

• Filing date: Jan 15, 2002
• Grant date: Mar 25, 2003
• Expiry date: Jan 15, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A configuration of at least two TSOP memory chip housings stacked one on another, is described. Each of the TSOP memory chip housings has at least one memory chip with a number of pins disposed in an interior of the TSOP memory chip housing. The pins leading out of a respective TSOP memory chip housing and, via a rewiring configuration, are connected to pins leading out of a respectively directly adjacent TSOP memory chip housing of the same TSOP memory chip housing stack. In order to be able to produce such a housing stack as cost-effectively and simply as possible by an automated mounting method, the rewiring configuration is implemented in the form of leadframes respectively disposed between or at the side between the individual TSOP memory chip housings.