Semiconductor integrated circuit
US6538924B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | May 30, 2001 |
| Grant date | Mar 25, 2003 |
| Priority date | — |
| Expiry date | May 30, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a semiconductor integrated circuit including a first storage having memory cells of a first configuration and a second storage having memory cells of a second configuration, according to a first combination (CS, RAS, CAS, and WE=“L” and A7=“0”) of control signals (CS, RAS, CAS, and WE) input to control terminals and at least a part of signals input to address terminals to which an address signal (A7) for selecting a memory cell in the first storage is input, an access to the first storage is instructed. According to a second combination (CS, RAS, CAS, WE=“L”, and A7=“1”) of the signals input to the control terminals and at least a part of signals input to the address terminals, an access to the second storage is instructed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.