Method for reducing the width of a global data bus in a memory architecture
US6538928B1 · kind B1 · utility
9Cited by
7References
24Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 11, 2000 |
| Grant date | Mar 25, 2003 |
| Priority date | — |
| Expiry date | Oct 11, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/3042
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory architecture uses shared sense amplifiers (18-23) and a centralized cache (26-29) that contains M bits. The memory architecture also includes a global bus (31) connecting the sense amplifiers and the centralized cache. The global bus includes n bits, and n<M bits are transferred in M/n cycles to the centralized cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.