Method and circuitry for identifying weak bits in an MRAM
US6538940B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2002 |
| Grant date | Mar 25, 2003 |
| Priority date | — |
| Expiry date | Sep 26, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory (10, 60) having at least two resistance states is tested. In one form, the memory includes a first transistor (16, 68) having a current electrode coupled to a memory cell (14, 64) and a second transistor (26, 66) having a current electrode coupled to a reference memory cell (28, 74). The control electrode of the first transistor receives either a first reference voltage or a second reference voltage based on a test control signal, and the control electrode of a second transistor receives the first reference voltage. In a test mode, after the memory cell is programmed with a resistance state, the second reference voltage (different from the first reference voltage) is provided to the first transistor. The memory cell is then read to determine whether the memory can sense the previously programmed resistance state. In one embodiment, this test mode can be used to identify weak bits in the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.