Device and method for maintaining time synchronous with a network master time
US6539049B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | May 28, 1999 |
| Grant date | Mar 25, 2003 |
| Priority date | — |
| Expiry date | May 28, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B2201/70709
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device includes a clock generator having a primary input for coupling to a primary reference frequency source, a secondary input for coupling to a secondary reference frequency source, and an output that produces a primary digital transceiver clock signal having a frequency of chiprate (S)(n) in a primary mode, and a secondiary digital transceiver clock signal having a frequency of chiprate in a secondary power saving mode. A chiprate divider connected to the output of the clock generator produces a primary mode enable signal that has a frequency of chiprate when in a primary mode. A long PN generator and a short PN generator each have a clock input that is coupled to the output of the clock generator. A first multiplexer output produces the primary mode enable signal in a primary mode, and the secondary mode enable signal in a secondary mode. A clock calibrator measures the frequency difference between 1/(S)(n) times the frequency of the primary digital transceiver clock signal and the frequency of the secondary digital transceiver clock signal as a function of time. A secondary mode timer indicates the amount of time the secondary mode is in effect. A contro…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.