Cache address conflict mechanism without store buffers
US6539457B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 21, 2000 |
| Grant date | Mar 25, 2003 |
| Priority date | — |
| Expiry date | Feb 21, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0897
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The inventive cache manages address conflicts and maintains program order without using a store buffer. The cache utilizes an issue algorithm to insure that accesses issued in the same clock are actually issued in an order that is consistent with program order. This is enabled by performing address comparisons prior to insertion of the accesses into the queue. Additionally, when accesses are separated by one or more clocks, address comparisons are performed, and accesses that would get data from the cache memory array before a prior update has actually updated the cache memory in the array are canceled. This provides a guarantee that program order is maintained, as an access is not allowed to complete until it is assured that the most recent data will be received upon access of the array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.