Method of developing re-usable software for efficient verification of system-on-chip integrated circuit designs

US6539522B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Robert J. Devins · South Burlington, US
• Paul G. Ferro · South Burlington, US
• Robert D. Herzl · South Burlington, US
• Mark E. Kautzman · Colchester, US
• Kenneth A. Mahler · Cincinnati, US
• David W. Milton · Underhill, US

Key dates

• Filing date: Jan 31, 2000
• Grant date: Mar 25, 2003
• Expiry date: Jan 31, 2020

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F30/33
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A method for developing re-usable software for the efficient verification of system-on-chip (SOC) integrated circuit designs. The verification software is used to generate and apply test cases to stimulate components of a SOC design (“cores”) in simulation; the results are observed and used to de-bug the design. The software is hierarchical, implementing a partition between upper-level test application code which generates test cases and verifies results, and low-level device driver code which interfaces with a core being simulated, to apply the test case generated by the upper-level code on a hardware level of operations. Test application and supporting low-level device driver pairs are used and re-used to test their corresponding component cores throughout the SOC development process, by creating higher-level test control programs which control selected combinations of the already-developed test application and device driver programs to test combinations of SOC components. The method provides for the efficient verification of SOC designs and, consequently, a reduced time-to-market for SOC products, because as the verification software is developed and stored, it becom…