Method and apparatus for determining capacitances for a device within an integrated circuit
US6539526B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 26, 2000 |
| Grant date | Mar 25, 2003 |
| Priority date | — |
| Expiry date | Apr 13, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (10) includes a device such as a transistor. A layout (90) of the device is prepared, which in the case of the transistor includes a ground plane section (52), spaced diffusion sections (56A-56B) and a gate section (57). In order to accurately identify all capacitances associated with the transistor, the gate section is subdivided into three subsections (57A-57C) which are treated as electrically separate, and the two diffusion sections are treated as electrically separate from structure external to the transistor that is electrically coupled to them. Capacitances are then identified between each pair of the electrically separate portions. Some of the identified capacitances may optionally be discarded. Capacitances identified for various portions that are actually in electrical contact are then summed in a specified manner, after which the summed capacitances are used to facilitate simulation of the operation of the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.