Method of designing, fabricating, testing and interconnecting an IC to external circuit nodes
US6539531B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2000 |
| Grant date | Mar 25, 2003 |
| Priority date | — |
| Expiry date | Mar 8, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30111
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for designing integrated circuits (ICs) and their interconnect systems includes IC component cells and interconnect component cells in a cell library. Each IC component cell provides both a physical and behavioral model of a component that may be incorporated into the IC while each interconnect component cell includes both a physical and behavioral model of a separate internal or external component of an interconnect system that may link the IC to external nodes. Both the IC and its interconnect systems are designed by selecting and specifying interconnections between component cells included in the cell library. Interconnect systems are flexibily designed to act like filters tuned to optimize desired frequency response characteristics. Behavior models of the IC and its interconnect systems, based on the behavior models of their selected component, are subjected to simulation and verification tools to determine whether the IC and its interconnect systems meet various performance criteria and constraints. The structural models of the interconnect systems developed during the design process guide subsequent fabrication of interconnect systems for both the IC's intended testi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.