Method for forming wafer level package
US6539624B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 1999 |
| Grant date | Apr 1, 2003 |
| Priority date | — |
| Expiry date | Mar 27, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49213
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a wafer level package that is equipped with solder balls on a top surface and encapsulated by a stress buffer layer of an elastomeric material is disclosed. The method can be carried by first forming a plurality of solder balls on bond pads provided on a top surface of a wafer and then forming an elastomeric material layer, or any other flexible, compliant material layer to encapsulate the solder balls. The tip portions of the solder balls is then substantially exposed by an etching process of either dry etching or wet etching such that the solder balls can be connected electrically to a circuit board. The present invention further provides a wafer level package that is formed with solder balls on a top surface encapsulated in an elastomeric material layer. The elastomeric material layer serves both as a stress buffer and a thermal expansion buffer such that the integrity and reliability of IC devices severed from the wafer can be maintained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.