Method of manufacturing a self-aligned gate transistor with P-type impurities selectively implanted below the gate, source and drain electrodes
US6541319B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 26, 2001 |
| Grant date | Apr 1, 2003 |
| Priority date | — |
| Expiry date | Dec 26, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/83
Abstract
The present invention provides a self-aligned gate transistor. The present invention implants P-type impurity ions only below a channel region below a gate and below a source and drain electrode on semiconductor substrate having an ion implantation channel layer without implanting the P-type impurity ions into a narrow region between the source-gate and the gate-drain, deposits a gate metal and etches the gate pattern. In this case, the length (Lg) of the gate is defined to be narrower than the length (Lch-g) into which P-type impurity ions are implanted below the channel layer, thus improving a pinch-off characteristic. A method of manufacturing a field effect transistor having a self aligned gate according to the present invention comprises the steps of implanting P-type impurity ions only below a channel region below a gate and below a source and drain electrode; and depositing a refractory gate metal having a good high temperature stability to form a gate pattern using a dry etch method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.