Methods of making field effect transistor structure with partially isolated source/drain junctions

US6541343B1 · kind B1 · utility

Assignee

• Intel Corporation · US

Inventors

• Anand S. Murthy · Beaverton, US
• Robert S. Chau · Beaverton, US
• Patrick Morrow · Portland, US
• Robert McFadden · Portland, US

Key dates

• Filing date: Dec 30, 1999
• Grant date: Apr 1, 2003
• Expiry date: Dec 30, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/116

Abstract

A microelectronic structure includes at least one source/drain terminal of a first conductivity type that is partially isolated from a region of semiconductor material of a second conductivity type. In a further aspect of the invention, a process for forming a microelectronic structure, such as a MOSFET, having at least one source/drain terminal of a first conductivity type that is partially isolated from a region of semiconductor material of a second conductivity type includes forming a recess having a surface, forming a dielectric material over a portion of the surface of the recess, and back-filling the recess to form a source/drain terminal.