Process for implementation of a hardmask
US6541387B1 · kind B1 · utility
0Cited by
1References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 17, 2002 |
| Grant date | Apr 1, 2003 |
| Priority date | — |
| Expiry date | Jan 17, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/952
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A resist layer is deposited atop a substrate and is patterned to expose portions of a substrate. A hardmask layer is deposited atop the patterned resist layer and atop the exposed portions of the substrate. The patterned resist layer is removed so that only a portion of the hardmask layer that is atop the substrate remains.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.