Method for fabricating a stacked chip package
US6541871B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2002 |
| Grant date | Apr 1, 2003 |
| Priority date | — |
| Expiry date | Mar 18, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a stacked chip package comprises the steps of: (a) attaching a first semiconductor chip to an upper surface of a substrate through a first adhesive layer; (b) partially curing the first adhesive layer such that it gels but does not harden; (c) attaching a second semiconductor chip to the first semiconductor chip through a second adhesive layer; (d) curing the first and second adhesive layer; (e) electrically coupling the first and second semiconductor chips to a structure for making external electrical connection provided on the substrate; and (f) forming a package body over the first semiconductor chip, the second semiconductor chip, and a portion of the upper surface of the substrate. Since the first and second adhesive layers may be cured in one single step, the cycle time may be reduced thereby cutting down the production cost.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.