Process for making and programming and operating a dual-bit multi-level ballistic flash memory
US6542412B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2002 |
| Grant date | Apr 1, 2003 |
| Priority date | — |
| Expiry date | Jan 28, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fast program, ultra-high density, dual-bit, multi-level flash memory process, which can be applied to a ballistic step split gate side wall transistor, or to a ballistic planar split gate side wall transistor, which enables low voltage requirement on the floating gate during erase is described. Two side wall floating gates are paired with a single word line select gate, and word lines are arranged to be perpendicular to both the bit lines and control gate lines. Adjacent memory cells on the same word line share bitline diffusion as well as a third poly control gate. Control gates allow erase access to the individual floating gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.