Redundant memory array having dual-use repair elements
US6542418B2 · kind B2 · utility
5Cited by
11References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2001 |
| Grant date | Apr 1, 2003 |
| Priority date | — |
| Expiry date | Jun 26, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/808
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit memory structure includes a main array of memory elements having wordlines and bitlines and a redundant array of redundant memory elements external to and connected to the main array. Each of the redundant memory elements can replace either one of the wordlines or one of the bitlines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.