Read port design and method for register array
US6542423B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2001 |
| Grant date | Apr 1, 2003 |
| Priority date | — |
| Expiry date | Sep 18, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/007
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A register array system including a first number of rows by a second number of columns of data registers, a read line, a read bit line, and a single pull down device corresponding to each data register in each column of data registers and configured to discharge, in response to being turned on, the read bit line corresponding to the column of data registers. The pull down device corresponding to a data register is only turned in response to a clock signal, a read enable signal, and the data stored in the data register each having a high value. Therefore, the capacitance associated with the read bit line corresponding to a column of data registers stays at the same capacitance value during the precharging phase and during a multi-hot condition. The problem of voltage droop caused by charging sharing in a multi-hot condition is thus eliminated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.