Method and apparatus for equalization of address transition detection pulse width
US6542435B1 · kind B1 · utility
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3References
18Claims
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Key dates
| Filing date | Mar 21, 2000 |
| Grant date | Apr 1, 2003 |
| Priority date | — |
| Expiry date | Mar 21, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus ensure equal address transition detection (ATD) pulse width for all address and chip enable transitions. Address buffer signals from one end of an integrated circuit are combined to form a first combined signal. Address buffer signals and a chip enable signal from a second end of the integrated circuit are combined to form a second combined signal. The two combined signals are logically combined to form a first edge of an ATD pulse. A feedback signal controls the second edge of the ATD pulse for all input signal transitions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.