Silent data corruption prevention due to instruction corruption by soft errors
US6543028B1 · kind B1 · utility
25Cited by
7References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2000 |
| Grant date | Apr 1, 2003 |
| Priority date | — |
| Expiry date | Mar 31, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/11
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique to detect and correct corruption of instructions by soft errors. A parity bit is propagated with an instruction through the instruction flow path and checked at selected places. When a parity error is detected, a replay circuit is used to perform a replay to reload the instruction to remove the corrupted instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.