Sujat Jamil
67Patents
15h-index
46Co-inventors
80Inventor score
Filing activity: Aug 6, 1998 → Mar 8, 2017
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7055060B2 | On-die mechanism for high-reliability processor | Physics | 53 | Expired |
| US6240510A | System for processing a cluster of instructions where the instructions are issued to the execution units having a priority order according to a template associated with the cluster of instructions | Physics | 51 | Expired |
| US8918625B1 | Speculative scheduling of memory instructions in out-of-order processor based on addressing mode comparison | Physics | 46 | Active |
| US6304960A | Validating prediction for branches in a cluster via comparison of predicted and condition selected tentative target addresses and validation of branch conditions | Physics | 43 | Expired |
| US8990505B1 | Cache memory bank selection | Emerging Cross-Sectional Technologies | 41 | Active |
| US9026769B1 | Detecting and reissuing of loop instructions in reorder structure | Physics | 40 | Active |
| US9223709B1 | Thread-aware cache memory management | Physics | 40 | Active |
| US7120755B2 | Transfer of cache lines on-chip between processing cores in a multi-core system | Physics | 28 | Expired |
| US6718494B1 | Method and apparatus for preventing and recovering from TLB corruption by soft error | Physics | 26 | Expired |
| US6543028B1 | Silent data corruption prevention due to instruction corruption by soft errors | Electricity | 25 | Expired |
| US6651145B1 | Method and apparatus for scalable disambiguated coherence in shared storage hierarchies | Physics | 25 | Expired |
| US8943273B1 | Method and apparatus for improving cache efficiency | Physics | 19 | Active |
| US9058272B1 | Method and apparatus having a snoop filter decoupled from an associated cache and a buffer for replacement line addresses | Emerging Cross-Sectional Technologies | 18 | Active |
| US7406553B2 | System and apparatus for early fixed latency subtractive decoding | Physics | 17 | Active |
| US6658621B1 | System and method for silent data corruption prevention due to next instruction pointer corruption by soft errors | Physics | 16 | Expired |
| US9934152B1 | Method and apparatus to use hardware alias detection and management in a virtually indexed physically tagged cache | Physics | 13 | Active |
| US8135916B1 | Method and apparatus for hardware-configurable multi-policy coherence protocol | Physics | 11 | Active |
| US8458404B1 | Programmable cache access protocol to optimize power consumption and performance | Emerging Cross-Sectional Technologies | 11 | Active |
| US7159077B2 | Direct processor cache access within a system having a coherent multi-processor protocol | Physics | 10 | Expired |
| US7100001B2 | Methods and apparatus for cache intervention | Emerging Cross-Sectional Technologies | 9 | Expired |
| US8806181B1 | Dynamic pipeline reconfiguration including changing a number of stages | Physics | 9 | Active |
| US6775748B2 | Methods and apparatus for transferring cache block ownership | Emerging Cross-Sectional Technologies | 9 | Expired |
| US9606800B1 | Method and apparatus for sharing instruction scheduling resources among a plurality of execution threads in a multi-threaded processor architecture | Physics | 8 | Active |
| US7917907B2 | Method and system for variable thread allocation and switching in a multithreaded processor | Physics | 8 | Active |
| US8631206B1 | Way-selecting translation lookaside buffer | Emerging Cross-Sectional Technologies | 8 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.