Method and apparatus for local resynthesis of logic trees with multiple cost functions
US6543032B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2000 |
| Grant date | Apr 1, 2003 |
| Priority date | — |
| Expiry date | Nov 26, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are systems and techniques for optimizing an integrated circuit design, in which a critical zone is identified in an integrated circuit design and a plurality of alternative identities are applied in the critical zone in order to obtain a corresponding plurality of outcomes. Alternative representations are then identified as those of the plurality of outcomes pursuant to which at least one of ramptime and timing are improved, and a best one of the alternative representations is selected to replace into the critical zone based on specified priorities which include: (i) selecting based on reduction in ramptime violation; (ii) selecting from among alternative representations that preserve cell area based on timing improvement; and (iii) if all alternative representations increase cell area, selecting based on an evaluation of a relationship between timing decrement and area increment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.