Elyar E. Gasanov
65Patents
11h-index
37Co-inventors
78Inventor score
Filing activity: Apr 17, 1998 → Nov 8, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6324674A | Method and apparatus for parallel simultaneous global and detail routing | Physics | 159 | Expired |
| US6175950A | Method and apparatus for hierarchical global routing descend | Physics | 118 | Expired |
| US6253363A | Net routing using basis element decomposition | Physics | 117 | Expired |
| US6550045B1 | Changing clock delays in an integrated circuit for skew optimization | Physics | 49 | Expired |
| US6550044B1 | Method in integrating clock tree synthesis and timing optimization for an integrated circuit design | Physics | 31 | Expired |
| US6564361B1 | Method and apparatus for timing driven resynthesis | Physics | 25 | Expired |
| US6543032B1 | Method and apparatus for local resynthesis of logic trees with multiple cost functions | Physics | 21 | Expired |
| US6637016B1 | Assignment of cell coordinates | Physics | 16 | Expired |
| US6845495B2 | Multidirectional router | Physics | 12 | Expired |
| US6629304B1 | Cell placement in integrated circuit chips to remove cell overlap, row overflow and optimal placement of dual height cells | Physics | 12 | Expired |
| US6681373B1 | Method and apparatus for dynamic buffer and inverter tree optimization | Physics | 12 | Expired |
| US6532582B1 | Method and apparatus for optimal critical netlist area selection | Physics | 11 | Expired |
| US10735138B2 | Multi-label offset lifting method | Electricity | 9 | Active |
| US6615401B1 | Blocked net buffer insertion | Physics | 8 | Expired |
| US8397143B2 | BCH or reed-solomon decoder with syndrome modification | Electricity | 7 | Active |
| US6637011B1 | Method and apparatus for quick search for identities applicable to specified formula | Physics | 7 | Expired |
| US9337866B2 | Apparatus for processing signals carrying modulation-encoded parity bits | Electricity | 6 | Active |
| US8176397B2 | Variable redundancy reed-solomon encoder | Electricity | 6 | Active |
| US6810515B2 | Process of restructuring logics in ICs for setup and hold time optimization | Physics | 6 | Expired |
| US6470487B1 | Parallelization of resynthesis | Physics | 5 | Expired |
| US8850437B2 | Two-pass linear complexity task scheduler | Physics | 5 | Active |
| US6701493B2 | Floor plan tester for integrated circuit design | Physics | 5 | Expired |
| US10594339B2 | Method for generating parity check matrix for low density parity check coding | Electricity | 4 | Active |
| US7401313B2 | Method and apparatus for controlling congestion during integrated circuit design resynthesis | Physics | 4 | Active |
| US9331716B2 | Systems and methods for area efficient data encoding | Physics | 4 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.