Annealing of high-k dielectric materials
US6544906B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2001 |
| Grant date | Apr 8, 2003 |
| Priority date | — |
| Expiry date | Oct 25, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for annealing a high dielectric constant (high-k) gate dielectric layer includes placing a wafer including one or more partially formed transistors in an ambient. The ambient may include hydrogen and an oxidizing gas or the ambient may include nitrous oxide. Each transistor includes a high-k gate dielectric layer coupled to a substrate. The method further includes heating the high-k gate dielectric layer to a temperature greater than 650° C. while the gate dielectric layer is in the ambient. The ambient prevents or reduces the formation of lower dielectric constant (lower-k) material between the high-k gate dielectric layer and the substrate. Another method for annealing a high-k gate dielectric layer includes the use of an ambient including chemically active oxygen gas. When such an ambient is used, the high-k gate dielectric layer is heated to a temperature not greater than 600° C. while the gate dielectric layer is in the ambient.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.