ELECTRONIC APPARATUS HAVING SEMICONDUCTOR DEVICE INCLUDING PLURALITY OF TRANSISTORS FORMED ON A POLYCRYSTALLINE LAYERED STRUCTURE IN WHICH THE NUMBER OF CRYSTAL GRAINS IN EACH POLYCRYSTALLINE LAYER IS GRADUALLY REDUCED FROM LOWER TO UPPER LAYER
US6545294B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2000 |
| Grant date | Apr 8, 2003 |
| Priority date | — |
| Expiry date | May 16, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/0251
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides an apparatus having a semiconductor device including a plurality of transistors formed on respective single crystal silicon regions of enlarged grain size. On a polycrystalline silicon layer, projections at regular intervals are formed by using anisotropic etching and a photomask. The tips of projections are composed of single crystal silicon of a specific crystal orientation selectively left by the anisotropic etching, which is a candidate for nuclei of amorphous silicon to be deposited thereon. By iterating the above process a plurality of times, and by gradually enlarging the pitch, span, size and height of projections, the size of the crystal grains of silicon at the surface may be enlarged to the extent required. Thereby, silicon crystal grains of large grain size with the crystal orientation aligned may be formed at controllable positions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.